1. Field of the Invention
The present invention relates generally to a semiconductor memory device having electrically rewritable nonvolatile memory cells having two-layer gate structure, and a method for producing the same. More specifically, the invention relates to the improvement of a process when peripheral circuits, such as logic circuits, are consolidated into a semiconductor memory device.
2. Related Background Art
A typical memory transistor of a nonvolatile semiconductor memory, such as an EEPROM, has a floating gate, which is formed on a semiconductor substrate via a gate insulating film, and a control gate which is formed on the floating gate via an insulating film. The memory transistor is combined with a selecting gate transistor to constitute a memory cell. In this case, the gate electrode of the selecting gate transistor is formed of the same gate electrode material film as that of the floating gate of the memory cell. In addition, when logic circuits, together with nonvolatile memory cells, are integrated to be formed, the gates of logic circuit transistors are formed of the same gate electrode material film as those of the control gates of the memory cells.
The semiconductor substrate, on which the memory cells and the logic circuit transistors have been formed, is covered with an interlayer dielectric film, and a metal wiring is formed thereon. The planarization of the interlayer dielectric film underlying the wiring is indispensable to the fine patterning of the wiring. In particular, when the wiring is formed in multilayer, the planarization of the interlayer dielectric film is indispensable. In recent years, the CMP (Chemical Mechanical Polishing) technique is often used for carrying out the planarization of the interlayer dielectric film.
When the planarization of the interlayer dielectric film is carried out by the CMP process, it is desired that the difference between the level of the two-layer gate structure portion of a memory cell array region and the level of the one-layer gate structure portion of a logic circuit is smaller from the point of view of the margin of contact and the prevention of short-circuit accident. In order to achieve this, it is considered that the first-layer gate electrode material film of the memory transistor and selecting gate transistor is thinned.
However, if the first-layer gate electrode material film is thin, the contact of the metal wiring easily goes through the gate electrode of the selecting gate transistor which is formed of the first-layer gate electrode material film. This causes the deterioration of yields and the deterioration of reliability due to the contact failure of the metal wiring to the selecting gate transistor.